1. Field of the Invention
The present invention relates to a digital system, and particularly, to a clock provided to a digital system.
2. Background of the Related Art
A clock used as an operating source in various digital circuits functions as a core of the circuit. Therefore, an accurate and stable clock frequency is required. In addition, as the digital circuit becomes faster and more precise, an accurate and stable clock becomes increasingly more important to reliable circuit operation. Moreover, in a field requiring high reliability such as communication equipment, multiple clock signals are used in order to address the problems of one clock generating source.
Hereinafter, a clock deciding apparatus according to the related art will be described with reference to accompanying FIG. 1. As shown therein, the related art clock deciding apparatus comprises: a phase locked loop (PLL) circuit 100 for converting a received frequency of a reference clock into a frequency used in the system; a multiplexer 140 for receiving a clock signal outputted from the PLL circuit 100 and an outer clock signal and outputting one of the two signals; an error detecting unit 110 for identifying whether or not there is an error in the received reference clock; a control unit 120 for outputting a predetermined control signal as referring to the test result of the error detecting unit 110 and a received outer control signal; and a clock selecting unit 130 for controlling the multiplexer 140 by decoding the control signal of the control unit 120.
The reference clock signal of a clock supplying source is transmitted to the PLL circuit 100 of the clock deciding apparatus, the PLL circuit 100 converts the frequency of the received reference clock into the frequency used in the system, and after that, transmits the signal to the multiplexer 140. Hereinafter, the reference clock signal outputted from the PLL circuit 100 is referred to as “P-reference clock signal”.
The error detecting unit 110 identifies whether there is an error on the received reference clock signal. Then, the result of the identification is notified to the control unit 120. The control unit 120 decides whether the clock deciding system including itself is a master or a slave referring to the outer control signal, and decides whether the reference clock signal is normal or abnormal referring to the result of the error detecting unit 110.
In addition, the control unit 120 outputs a predetermined signal for controlling the multiplexer 140 to the clock selecting unit 130 based on the decision. The clock selecting unit 130 outputs the control signal of the control unit 120 to the multiplexer 140 after decoding it. In addition, according to the control of the clock selecting unit 130, the multiplexer 140 selects one of the P-reference clock signal and the outer clock signal, and outputs the selected one.
The two apparatuses (dock deciding apparatuses A and B) having a dual structure, as described above, perform the same operation. However, these apparatuses are in a complementary relationship with each other. If the clock signal of the apparatus A is abnormal, apparatus A receives the clock signal of apparatus B through a path connected to apparatus B and outputs it. Therefore, it is able to provide the system with a stable and continuous clock signal.
However, according to the related art device, it takes a lot of time for locking the PLL circuit. Also, if the time points of PLL locking in the clock deciding apparatus A and the clock deciding apparatus B are different from each other, the phases of the clock signals outputted from the two deciding apparatuses are different. The above problem causes degradation of the clock signal provided to the system since the duty is changed rapidly at the time when the dual switching is generated. In the digital circuits and systems, the degradation of the clock signal can cause a fatal error.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.